1. Field of the Invention
This disclosure relates to a semiconductor device and method for fabricating the same and, more particularly, to a semiconductor device having two different operation modes employing an asymmetrical buried oxidation layer and method for fabricating the same
2. Description of the Related Art
Semiconductor devices employing a discrete device such as a metal oxide semiconductor (MOS) transistor as a switching device are widely used. Since the degree of integration of semiconductor devices is steadily increasing, the size of MOS transistors are correspondingly being scaled down. As a result, shortened channel lengths of the MOS transistors may cause short channel effect (SCE). In order to reduce the SCE, channel ion concentration is inevitably increased. However, the increased channel ion concentration also causes a leakage current to increase. Increased leakage current leads to deterioration of the refresh characteristic of the DRAM device.
In an effort to reduce SCE, research has been conducted for transistors having a silicon-on-insulator (SOI) structure. The SOI structure includes a lower semiconductor substrate, an upper silicon pattern, and a buried insulating layer between them for insulating the lower semiconductor substrate from the upper silicon pattern. Transistors having the SOI structure may reduce the SCE and parasitic capacitance, operate at high speed, and reduce power consumption. However, they allow floating body effects, for example, kink effects, to occur.
To cope with the problems related to floating body effects, various methods have been proposed to electrically connect the upper silicon pattern to the lower semiconductor substrate. For example, a method for electrically connecting the upper silicon pattern to the lower semiconductor substrate is disclosed in U.S. Pat. No. 6,429,091 to Chen et al. (“Chen”) entitled “Patterned Buried Insulator.”
According to Chen, a mask is formed on a semiconductor substrate to form buried doping regions beneath source/drain regions. After the doping regions are selectively etched, an insulator is filled in the etched portion to form buried insulating layers. A transistor having the source/drain regions positioned on the buried insulating layers is then formed. As a result, patterned buried insulating layers that reduced junction leakage current are formed beneath the source/drain regions. In addition, the transistor is electrically connected to the semiconductor substrate below the buried insulating layer to operate in a body-tied mode, which reduces the floating-body effect.
However, because the semiconductor device fabricated by the method disclosed by Chen operates in the body-tied mode, the on-current and off-current is decreased and increased, respectively, compared to the MOS transistor having the SOI structure.
Embodiments of the invention address these and other disadvantages of the conventional art.